Motor Drive Power Management Architecture

The Accelerator architecture is positioned between the micro- or DSP-controller and the motor to enhance and simplify DSP and microprocessor-controlled motion control circuits. By simplifying motor drive power management, more design effort can be concentrated on the main control algorithm and man-machine interface.

The new chip set architecture consists of mixed signal 0.5µm CMOS and high voltage ICs with ratings from 600 to 1200V. The architecture can be applied to AC induction motors, as well as brushless DC motors. Typical applications include industrial AC drives, industrial servo drives, compressor drives, washing machines, electric power steering, integrated starter alternators and high reliability drives. It simplifies power management design and increases reliability by reducing total parts count by 25%, and cutting circuit board footprint by 50%. Motor drives using this architecture can easily fit within the dimensions of the industry-standard ECONO2 package outline, approximately 4.25 x 1.75 x 0.62 in. (L x W x H).

The chip set integrates analog and interface functions and features a dual port memory with serial interface I/O. It includes versatile diagnostic functions, dead time generation and dead time compensation functions. The chip set can be programmed by a user-defined PWM or a built-in, optional space vector PWM generator.

The high voltage ICs are rated at 600V for 230VAC drive circuits and 1200V for 460VAC drive circuits. The gate drivers are designed with matched delays to enable very small dead time. Optimized dead time compensation, based on voltage sensing, delivers a ten times more useable speed range. Current sensing delivers 1% accuracy for better torque precision. Robust protection against ground fault and line-to-line short circuits helps ensure high system reliability. IR MOSFETs and IGBTs in industry-standard or application-specific packages work with the analog portion of motion control circuits.

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